1. Field of the Invention
This invention relates to a semiconductor memory device and data writing method thereof, and more particularly relates to a non-volatile semiconductor memory device capable of establishing multi-level information and a voltage control method for writing such information.
2. Description of the Related Art
A non-volatile semiconductor memory device has a plurality of memory cell. The memory cell has an electrode called as floating gate which is insulated electrically from a gate electrode called as control gate thereof and a silicon substrate.
Data are written in a memory cell transistor by two ways. One is a writing method (referred to as FN wiring method hereinafter) in which the control gate is maintained at a high voltage, and electrons are pulled out from the floating gate by way of tunnel current to lower the threshold voltage (referred to as cell Vt hereinafter) of the memory cell. The other one is a writing method (referred to as CHE writing method hereinafter) in which channel hot electrons are generated by a current flowing between the drain and the source by the condition that the control gate is maintained at a high voltage and the drain is maintained at a medium voltage are transferred to the floating gate to raise the cell Vt.
CHE writing method is advantageous in comparison with FN writing method in that a short time is sufficient for writing. Therefore CHE writing method has attracted attentions recently.
Recently, the demand for large memory capacity of memory IC has grown more and more. To satisfy the demand, use of multi-level information of three or higher level to be stored in memory cells has been developed.
Japanese Patent Laid-open No. Hei 7-29382 proposes a means for writing such multi-level information of three or higher level in a memory cell by way of CHE writing method.
However, the writing method involves transitional cell Vt instead of final or saturate cell Vt as multi-level information to be stored in the memory cell. Therefore, dispersion in writing characteristics of the memory cell should be concerned. The width of cell Vt distribution is wide and writing operation margin is small.